Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning

We discuss the implementation and evaluation of move-based hypergraph partitioning heuristics in the context of VLSI design applications. Our rst contribution is a detailed software architecture, consisting of seven reusable components, that allows exible, e cient and accurate assessment of the practical implications of new move-based algorithms and partitioning formulations. Our second contribution is an assessment of the modern context for hypergraph partitioning research for VLSI design applications. In particular, we discuss the current level of sophistication in implementation know-how and experimental evaluation, and we note how requirements for real-world partitioners { if used as motivation for research { should a ect the evaluation of prospective contributions. We then use two \implicit decisions" in the implementation of the Fiduccia-Mattheyses [20] heuristic to illustrate the di culty of achieving meaningful experimental evaluation of new algorithmic ideas. Finally, we provide anecdotal evidence that our proposed software architecture is conducive to algorithm innovation and leading-edge quality of results.